1 `define ST_STOP 3'b001
2 `define ST_GO 3'b010
3 `define ST_SLOW 3'b100
4
5 module main;
6
7 reg clk;
8 reg go;
9 wire [2:0] state;
10
11 fsma fsm1( clk, go, state );
12 fsmb fsm2( clk, go );
13
14 wire error = (state[0] & state[1]) || (state[0] & state[2]) || (state[1] & state[2]) || (state == 3'b000);
15
16 initial begin
17 $dumpfile( "example.vcd" );
18 $dumpvars( 0, main );
19 go = 1'b0;
20 repeat( 10 ) @(posedge clk);
21 go = 1'b1;
22 #10;
23 $finish;
24 end
25
26 initial begin
27 clk = 1'b0;
28 forever #(1) clk = ~clk;
29 end
30
31 endmodule
32
33 module fsma( clk, go, state );
34
35 input clk;
36 input go;
37 output [2:0] state;
38
39 reg [2:0] next_state;
40 reg [2:0] state;
41
42 initial begin
43 state = `ST_SLOW;
44 end
45
46 always @(posedge clk) state <= next_state;
47
48 (* covered_fsm, lights, is="state", os="next_state" *)
49 always @(state or go)
50 case( state )
51 `ST_STOP : next_state = go ? `ST_GO : `ST_STOP;
52 `ST_GO : next_state = go ? `ST_GO : `ST_SLOW;
53 `ST_SLOW : next_state = `ST_STOP;
54 endcase
55
56 endmodule
57
58 module fsmb( clk, go );
59
60 input clk;
61 input go;
62
63 reg [2:0] next_state;
64 reg [2:0] state;
65
66 initial begin
67 state = `ST_STOP;
68 end
69
70 always @(posedge clk) state <= next_state;
71
72 (* covered_fsm, lights, is="state", os="next_state",
73 trans="3'b001->3'b010",
74 trans="3'b010->3'b100",
75 trans="3'b100->3'b001" *)
76 always @(state or go)
77 case( state )
78 `ST_STOP : next_state = go ? `ST_GO : `ST_STOP;
79 `ST_GO : next_state = go ? `ST_GO : `ST_SLOW;
80 `ST_SLOW : next_state = `ST_STOP;
81 endcase
82
83 endmodule