1 ::::::::::::::::::::::::::::::::::::::::::::::::::
2 :: ::
3 :: Covered -- Verilog Coverage Verbose Report ::
4 :: ::
5 ::::::::::::::::::::::::::::::::::::::::::::::::::
6
7
8 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GENERAL INFORMATION ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 * Report generated from CDD file : cov.cdd
12
13 * Reported by : Module
14
15 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ LINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
17 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 Module/Task/Function Filename Hit/ Miss/Total Percent hit
19 ---------------------------------------------------------------------------------------------------------------------
20 main example.v 3/ 0/ 3 100%
21 fsma example.v 4/ 0/ 4 100%
22 fsmb example.v 3/ 1/ 4 75%
23 ---------------------------------------------------------------------------------------------------------------------
24
25 Module: fsmb, File: example.v
26 -------------------------------------------------------------------------------------------------------------
27 Missed Lines
28
29 80: next_state = 3'b1
30
31
32
33 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
34 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TOGGLE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
35 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
36 Module/Task/Function Filename Toggle 0 -> 1 Toggle 1 -> 0
37 Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
38 ---------------------------------------------------------------------------------------------------------------------
39 main example.v 4/ 2/ 6 67% 3/ 3/ 6 50%
40 fsma example.v 5/ 3/ 8 62% 4/ 4/ 8 50%
41 fsmb example.v 4/ 4/ 8 50% 3/ 5/ 8 38%
42 ---------------------------------------------------------------------------------------------------------------------
43
44 Module: main, File: example.v
45 -------------------------------------------------------------------------------------------------------------
46 Signals not getting 100% toggle coverage
47
48 Signal Toggle
49 ---------------------------------------------------------------------------------------------------------
50 go 0->1: 1'h1
51 ......................... 1->0: 1'h0 ...
52 state 0->1: 3'h3
53 ......................... 1->0: 3'h5 ...
54 error 0->1: 1'h0
55 ......................... 1->0: 1'h0 ...
56
57 Module: fsma, File: example.v
58 -------------------------------------------------------------------------------------------------------------
59 Signals not getting 100% toggle coverage
60
61 Signal Toggle
62 ---------------------------------------------------------------------------------------------------------
63 go 0->1: 1'h1
64 ......................... 1->0: 1'h0 ...
65 state 0->1: 3'h3
66 ......................... 1->0: 3'h5 ...
67 next_state 0->1: 3'h2
68 ......................... 1->0: 3'h1 ...
69
70 Module: fsmb, File: example.v
71 -------------------------------------------------------------------------------------------------------------
72 Signals not getting 100% toggle coverage
73
74 Signal Toggle
75 ---------------------------------------------------------------------------------------------------------
76 go 0->1: 1'h1
77 ......................... 1->0: 1'h0 ...
78 next_state 0->1: 3'h2
79 ......................... 1->0: 3'h1 ...
80 state 0->1: 3'h2
81 ......................... 1->0: 3'h1 ...
82
83
84 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ COMBINATIONAL LOGIC COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
86 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
87 Module/Task/Function Filename Logic Combinations
88 Hit/Miss/Total Percent hit
89 ---------------------------------------------------------------------------------------------------------------------
90 main example.v 10/ 8/ 18 56%
91 fsma example.v 8/ 4/ 12 67%
92 fsmb example.v 8/ 4/ 12 67%
93 ---------------------------------------------------------------------------------------------------------------------
94
95 Module: main, File: example.v
96 -------------------------------------------------------------------------------------------------------------
97 Missed Combinations (* = missed value)
98
99 =========================================================================================================
100 Line # Expression
101 =========================================================================================================
102 14: error = ((state[0] & state[1]) || (state[0] & state[2]) || (state[1] & state[2]) || (state == 3'b0))
103 |---------1---------| |---------2---------| |---------3---------| |------4------|
104 |--------------------------------------------5---------------------------------------------|
105
106 Expression 1 (2/3)
107 ^^^^^^^^^^^^^ - &
108 LR | LR | LR
109 =0-=|=-0=|=11=
110 *
111
112 Expression 2 (2/3)
113 ^^^^^^^^^^^^^ - &
114 LR | LR | LR
115 =0-=|=-0=|=11=
116 *
117
118 Expression 3 (2/3)
119 ^^^^^^^^^^^^^ - &
120 LR | LR | LR
121 =0-=|=-0=|=11=
122 *
123
124 Expression 4 (1/2)
125 ^^^^^^^^^^^^^ - ==
126 E | E
127 =0=|=1=
128 *
129
130 Expression 5 (1/5)
131 ^^^^^^^^^^^^^ - ||
132 1 | 2 | 3 | 4 | All
133 =1=|=1=|=1=|=1=|==0==
134 * * * *
135
136
137 Module: fsma, File: example.v
138 -------------------------------------------------------------------------------------------------------------
139 Missed Combinations (* = missed value)
140
141 =========================================================================================================
142 Line # Expression
143 =========================================================================================================
144 51: case( state )
145 |-1-|
146 3'b1 :
147
148 Expression 1 (1/2)
149 ^^^^^^^^^^^^^ -
150 E | E
151 =0=|=1=
152 *
153
154 =========================================================================================================
155 Line # Expression
156 =========================================================================================================
157 51: next_state = go ? 3'b10 : 3'b1
158 |-------1--------|
159
160 Expression 1 (1/2)
161 ^^^^^^^^^^^^^ - ?:
162 E | E
163 =0=|=1=
164 *
165
166 =========================================================================================================
167 Line # Expression
168 =========================================================================================================
169 52: next_state = go ? 3'b10 : 3'b100
170 |1|
171 |--------2---------|
172
173 Expression 1 (1/2)
174 ^^^^^^^^^^^^^ -
175 E | E
176 =0=|=1=
177 *
178
179 Expression 2 (1/2)
180 ^^^^^^^^^^^^^ - ?:
181 E | E
182 =0=|=1=
183 *
184
185
186 Module: fsmb, File: example.v
187 -------------------------------------------------------------------------------------------------------------
188 Missed Combinations (* = missed value)
189
190 =========================================================================================================
191 Line # Expression
192 =========================================================================================================
193 78: case( state )
194 |-1-|
195 3'b1 :
196
197 Expression 1 (1/2)
198 ^^^^^^^^^^^^^ -
199 E | E
200 =0=|=1=
201 *
202
203 =========================================================================================================
204 Line # Expression
205 =========================================================================================================
206 78: next_state = go ? 3'b10 : 3'b1
207 |-------1--------|
208
209 Expression 1 (1/2)
210 ^^^^^^^^^^^^^ - ?:
211 E | E
212 =0=|=1=
213 *
214
215 =========================================================================================================
216 Line # Expression
217 =========================================================================================================
218 79: next_state = go ? 3'b10 : 3'b100
219 |1|
220 |--------2---------|
221
222 Expression 1 (1/2)
223 ^^^^^^^^^^^^^ -
224 E | E
225 =0=|=1=
226 *
227
228 Expression 2 (1/2)
229 ^^^^^^^^^^^^^ - ?:
230 E | E
231 =0=|=1=
232 *
233
234
235
236 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
237 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ FINITE STATE MACHINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
238 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
239 State Arc
240 Module/Task/Function Filename Hit/Miss/Total Percent Hit Hit/Miss/Total Percent hit
241 ---------------------------------------------------------------------------------------------------------------------
242 main example.v 0/ 0/ 0 100% 0/ 0/ 0 100%
243 fsma example.v 3/ ? / ? ? % 4/ ? / ? ? %
244 fsmb example.v 2/ 1/ 3 67% 3/ 2/ 5 60%
245 ---------------------------------------------------------------------------------------------------------------------
246
247 Module: fsma, File: example.v
248 -------------------------------------------------------------------------------------------------------------
249 FSM input state (state), output state (next_state)
250
251 Hit States
252
253 States
254 ======
255 3'h4
256 3'h1
257 3'h2
258
259 Hit State Transitions
260
261 From State To State
262 ========== ==========
263 3'h4 -> 3'h1
264 3'h1 -> 3'h1
265 3'h1 -> 3'h2
266 3'h2 -> 3'h2
267
268
269 Module: fsmb, File: example.v
270 -------------------------------------------------------------------------------------------------------------
271 FSM input state (state), output state (next_state)
272
273 Missed States
274
275 States
276 ======
277 3'h4
278
279 Missed State Transitions
280
281 From State To State
282 ========== ==========
283 3'h2 -> 3'h4
284 3'h4 -> 3'h1
285
286
287