Line coverage is the quickest way to determine what logic in your design is being exercised and which logic has not be exercised during simulation. If a line was found to not be simulated, this is an indication that there was some event that did not occur or did not occur at the proper time to cause a previous conditional expression to be evaluated to true or false. For example, if a block of code looked something like:
Line | Logic |
---|---|
1 | always @(posedge clock) |
2 | if( a ) |
3 | b <= 1'b0; |
4 | else |
5 | b <= 1'b1; |
If line 3 was shown to be not covered, this would indicate that at the positive edge of the term "clock", the value of "a" never evaluated to a value of 1 (true). To make line 3 become covered, we would need to setup a situation in the diagnostic that caused "a" to become true at the positive edge of the term "clock".
On the other hand, if all lines 2 - 5 were found to be uncovered, this would indicate the the term "clock" never made a transition from some value to a 1 (true) value during simulation.
To view line coverage for all uncovered lines for a specific module/instance, do the following:
Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the uncovered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to not be hit during the simulation of this module/instance.
To view line coverage for all covered lines for a specific module/instance, do the following:
Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the covered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to be hit during the simulation of this module/instance.
You may see both the covered and uncovered line coverage simultaneously by selecting both the "Show Uncovered" and "Show Covered" items in the Report menu. This is sometimes useful to see what logic Covered was not able to provide coverage support for (all lines which contain code that are not highlighted in either the uncovered or covered color schemes).