Covered - The Verilog Code Coverage Analyzer

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Navigating the Line Coverage Window


Line coverage is the quickest way to determine what logic in your design is being exercised and which logic has not be exercised during simulation. If a line was found to not be simulated, this is an indication that there was some event that did not occur or did not occur at the proper time to cause a previous conditional expression to be evaluated to true or false. For example, if a block of code looked something like:

LineLogic
1always @(posedge clock)
2  if( a )
3    b <= 1'b0;
4  else
5    b <= 1'b1;

If line 3 was shown to be not covered, this would indicate that at the positive edge of the term "clock", the value of "a" never evaluated to a value of 1 (true). To make line 3 become covered, we would need to setup a situation in the diagnostic that caused "a" to become true at the positive edge of the term "clock".

On the other hand, if all lines 2 - 5 were found to be uncovered, this would indicate the the term "clock" never made a transition from some value to a 1 (true) value during simulation.

Viewing Uncovered Lines

To view line coverage for all uncovered lines for a specific module/instance, do the following:

  1. Make sure that the "Show Uncovered" menu item in the Report menu is selected.
  2. Select the line coverage metric in the Coverage Type Bar by left-clicking on selection button to the left of "Line".
  3. Select one of the modules/instances that is highlighted in the uncovered color scheme (to change this color scheme, see Preferences Menu) in the Module/Instance Listbox. This will cause the selected module/instance source code to be displayed in the Coverage File Viewer.

Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the uncovered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to not be hit during the simulation of this module/instance.

Viewing Covered Lines

To view line coverage for all covered lines for a specific module/instance, do the following:

  1. Make sure that the "Show Covered" menu item in the Report menu is selected.
  2. Select the line coverage metric in the Coverage Type Bar by left-clicking on the selection button to the left of "Line".
  3. Select one of the modules/instances in the Module/Instance Listbox that shows that at least one line was considered coverable by Covered by looking in the Coverage Summary Bar.

Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the covered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to be hit during the simulation of this module/instance.

Important Note

You may see both the covered and uncovered line coverage simultaneously by selecting both the "Show Uncovered" and "Show Covered" items in the Report menu. This is sometimes useful to see what logic Covered was not able to provide coverage support for (all lines which contain code that are not highlighted in either the uncovered or covered color schemes).