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To properly evaluate the effectiveness of any coverage tool, it is necessary to understand what kinds of logic are able to be analyzed and which kinds of logic are unable to be analyzed (along with a reason for why the logic cannot be adequately covered). Understanding the limitations of tools up front can often guide the user of those tools to make better decisions in their usage. In the case of Covered and the open source community, it may also help drive ideas to how to correct or get around these limitations. |
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For these reasons, a list of what type of logic can be analyzed and what type of logic cannot be currently analyzed is listed below. Note that both of these lists may not be exhaustive and are subject to change between releases of the tool. Also note that it is the goal of Covered to be able to parse all of the Verilog-1995 and Verilog-2001 constructs though some portions of it may be ignored for coverage purposes. |
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When logic is encountered that cannot be analyzed within an always, initial, task, function or named block, Covered will disregard the entire always block. If the entire block cannot be analyzed, it does not try to get coverage statistics as these will most likely be incorrect (i.e., disregarded logic could affect the state of the logic that is being covered). |
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