Stack Class Reference

Draw a Stack of Transistors. More...

Public Member Functions
	__init__ (self, device, NERC, NIRC)
	[API] Constructor
	setWirings (self, wiringSpec)
	[API] Set the Stack wiring specification.
	computeDimensions (self)
	[internal] Compute Stack dimensions from the technological rules.
	doLayout (self, bbMode)
	[API] Draw the complete layout.

Detailed Description

Draw a Stack of Transistors.

A Stack of Transistors is a set of transistor put into a regular band and connected through their sources/drains. All share the exact same W & L. The way they are connecteds defines what functionnality the Stack implement.

The abutment box of the stack is adjusted so that both height and width are even multiples of the track pitches, so the device can be easily placed and handled by the mixed router. The extra space needed for padding is added around the active area. Due to the presence of tracks at the top and bottom of the stack, the active area will be horizontally centered but not vertically.

The drawing of the stack is controlled through a set of variables (attributes) that allows to create it regardless of the technology. The technology is taken into account in the way those variables are computed and, obviously, their values. The following schematics details the main stack drawing variables along with their computations.

Stack Layout

Gate pitch

• self.gatePitch : the pitch of transistors gates, inside the stack. It also applies to dummy transistors.

Gate Pitch

Active Side Width

• self.activeSideWidth : the distance between the axis of the last transistor gate (on the left or right) and the edge of the active area (not the diffusion area).

Active Side Width

H-Track Distance

• self.hTrackDistance : the minimal distance between either the top or bottom edge of the active area and the axis of the first track.

H-Track distance

BoundingBox & Overall Variables

• self.xpitches : the number of vertical track pitches needed to fully enclose the active area.
• self.ypitches : the number of horizontal track pitches needed to fully enclose the active area.
• self.activeOffsetX & self.activeOffsetY : the offsets of the active area from the bottom left corner of the abutment box.
• self.diffusionWidth & self.diffusionHeight are the minimun dimensions required to fit the active area.
• self.topTracksNb() : the number of tracks at the top of the stack.
• self.botTracksNb() : the number of tracks at the bottom of the stack.

General Stack Layout

Wiring Specifications

Stack routing is done through vertical metal1 wires coming from the gates and diffusions areas and metal2 horizontal wires that can be either above or below the active area. metal2 wires (or track) goes through the whole stack and are assigned to one net only. A net will have at least one track above or below and may have both.

The connections to the diffusions areas and gates of the various fingers are specified through a list. The stack is made of a regular alternation of diffusions and gates. The list tells, for each one starting from the left, to which net and track they are connected. For a stack of transistor fingers, the must wiring specification must contains elements. The list is given through one string with each elements separated by one or more whitespace. The syntax for one element is detailed Atomic Wiring Specification.

Track numbering scheme

Tracks above (top) the active area and below (bottom) each have their own numbering. In both case, the count start from the active area. This, the top tracks will be numbered by increasing Y and the bottom tracks by decreasing Y.

Track/Net assignement

The track/net assignement is deduced from the atomic wiring specifications. It also allows to compute the total number of tracks needed above and below the active area.

Wiring Specification

Atomic Wiring Specification

An atomic wiring specification has the same syntax for either diffusions or gates. It must not comprise any whitespaces. it is made of the following parts:

• The net name to connect to.
• Whether the track is above the active area ("t") or below ("b"). The special case ("z") means that this element must be left unconnected (is such case possible?).
• The number of the track.

Atomic Wiring Specification

Stack Implementation Details

The __setattr__() and __getattr__ functions have been redefined so that the technological values (rules) can be accessed has normal attributes of the Stack class, in addition to the regular ones.

Constructor & Destructor Documentation

__init__()

__init__	(		self,
			device,
			NERC,
			NIRC )

[API] Constructor

param rules The physical rule set.

Parameters

device	The Hurricane AMS device into which the layout will be drawn.
NERC	Number of contact rows in external (first & last) diffusion connectors.
NIRC	Number of contact rows in middle diffusion connectors. param w The width of every transistor of the stack (aka fingers). param L The length of every transistor. param NFs The total number of fingers (dummies includeds). param NDs The number of dummies to put on each side of the stack.

References bImplantLayer, botTracks, botWTracks, bulkNet, bulks, device, dimensioned, Bulk.flags, flags, isNmos(), L, metaTnb(), metaTransistors, NDs, NERC, NFs, NIRC, tImplantLayer, topTracks, topWTracks, w, wellLayer, and wirings.

Member Function Documentation

setWirings()

setWirings	(		self,
			wiringSpec )

[API] Set the Stack wiring specification.

Parameters

wiringSpec

A string defining the connections for the gates and diffusion areas.

For a comprehensive explanation of the wiring specification, refers to Wiring Specifications .

References botTracks, botTracksNb(), botWTracks, bulkNet, computeDimensions(), device, dimensioned, eDiffMetal1Width, Bulk.flags, flags, gatePitch, getBotTrackY(), getHorizontalWidth(), horPitch, L, metal1ToGate, metaTransistors, sideActiveWidth, topTracks, topTracksNb(), topWTracks, wirings, and ypitches.

computeDimensions()

computeDimensions

(

self

)

[internal] Compute Stack dimensions from the technological rules.

Internal function. Perform the computation of:

• self.metal1Pitch
• self.minWidth_metal1
• self.metal2Pitch
• self.minWidth_metal2
• self.gatePitch
• self.sideActiveWidth
• self.hTrackDistance
• self.xpitches
• self.ypitches
• self.activeOffsetX
• self.activeOffsetY
• self.boundingBox

References activeBox, activeOffsetX, activeOffsetY, bbHeight, bbWidth, botWTracks, boundingBox, bulks, bulkWidth, computeLayoutParasitics(), computeStressEffect(), contactDiffPitch, contactDiffSide, DGG, DGI, dimensioned, DMCG, DMCGT, DMCI, eDiffMetal1Width, Bulk.flags, flags, gatePitch, gateVia1Pitch, getBotTrackY(), getHorizontalWidth(), getLastTopTrackY(), horPitch, hTrackDistance, iDiffMetal1Width, isVH, L, metal1ToGate, metal2Pitch, metal2TechnoPitch, metal3Pitch, metaTransistors, minEnclosure_active_cut0, minEnclosure_tImplant_active, minWidth_cut0, minWidth_cut1, NERC, NFs, NIRC, sideActiveWidth, tracksNbPitch(), vBulkDistance, verPitch, w, wire1Width, wire2Width, wire3Width, wirings, xpitches, and ypitches.

Referenced by CapacitorUnit.create(), doLayout(), RoutMatchedCapacitor.route(), and setWirings().

doLayout()

doLayout	(		self,
			bbMode )

[API] Draw the complete layout.

Draw the commplete layout of the Stack.

References activeOffsetX, activeOffsetY, bbWidth, botTracks, botWTracks, boundingBox, bulkNet, bulks, bulkWidth, computeDimensions(), contactDiffPitch, device, DGG, DGI, DMCG, DMCGT, DMCI, drawActive(), drawGate(), drawSourceDrain(), drawWell(), eDiffMetal1Width, Bulk.flags, flags, gatePitch, gateVia1Pitch, getBotTrackY(), getHorizontalAxis(), getHorizontalWidth(), getTopTrackY(), getWiringWidth(), horPitch, iDiffMetal1Width, isBotTrack(), isVH, L, metal1ToGate, minEnclosure_active_cut0, minEnclosure_metal2_cut2, minEnclosure_tImplant_active, minWidth_cut0, minWidth_cut1, minWidth_cut2, NERC, NFs, NIRC, sideActiveWidth, tImplantLayer, topTracks, topWTracks, w, wellLayer, wire1Width, wire2Width, wire3Width, and wirings.

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The documentation for this class was generated from the following file:

• stack.py