VerticalRoutingTracks Class Reference

Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. More...

Inheritance diagram for VerticalRoutingTracks:

Public Member Functions
	__setStretching__ (self)
	Sets vertical stretching value considering spacing between elementary capacitors in the matrix.
	setRules (self)
	Defines technology rules used to draw the layout.
	create (self)
	Draw the compact or matrix of capacitors.
	drawVRoutingTracks (self, vRoutingTracksLayer)
	Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer.
Public Member Functions inherited from CapacitorStack
	__init__ (self, device, capacitance, capacitorType, abutmentBoxPosition, nets, unitCap=0, matrixDim=[1, 1], matchingMode=False, matchingScheme=[], dummyRing=False, dummyElement=False)
	This is the class constructor.
	__isUnitCap__ (self)
	__isMatchingSchemeOK__ (self)
	capacitorIdOccurence (self, capacitorIdentifier)
	capacitorLine (self, dy, abutmentBox_spacing, matchingSchemeRowIndex=0)
	Iteratively draws a horizontal or vertical line of capacitors according to the direction parameter.
	capacitorMatrix (self, abutmentBox_spacing=0)
	Draws a matrix of identical capacitors.
	drawAbutmentBox (self, abutmentBox_spacing=0)
	Draws the abutment box of the matrix or campact capacitor.
	drawBottomPlatesRLayers (self, bottomPlateRLayer, drawnCapacitor)
	Draws the routing layers connecting the bottom plate in the matrix of capacitors.
	drawTopPlatesRLayers (self, topPlateRLayer, drawnCapacitor)
	Draws the routing layers connecting the top plates in the matrix of capacitors.
	getVerticalRoutingTrack_width (self)
	getMatrixDim (self)
	getMatchingScheme (self)
Public Member Functions inherited from CapacitorUnit
	__init__ (self, device, capacitorType, abutmentBoxPosition, capacitance=0, capDim={})
	This is the class constructor.
	__setCapacitorPerUnit__ (self, capacitorType)
	Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType (MIM or PIP).
	__computeCapDim__ (self, capacitance, capacitorType)
	Computes width and length of the capacitor.
	__isCapacitorUnitOK__ (self, capDim)
	Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules.
	getCapacitorType (self)
	getMaximumCapWidth (self)
	getMinimumCapWidth (self)
	getLayers (self)
	Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP).
	drawCapacitor (self, layerDict, t, b)
	Draws all layout physicial layers of the capacitor.
	computeBottomPlateCuts (self)
	Computes needed parameters to draw bottom plate cuts in its exact position, including :
	computeTopPlateCuts (self)
	Computes needed parameters to draw top plate cuts in its exact position, including :
	drawOnePlate (self, layer, net, boxDimensions)
	Draws the top or bottom plate through inflation of the Box under it.
	drawBottomPlateCut (self, layer, b)
	Draws the required cuts to connect the bottom plate.
	drawTopPlateCut (self, layer, t)
	Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate.
	drawRoutingLayers (self, bottomPlateLayer, topPlateLayer, t, b)
	Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers.
	cutMaxNumber (self, width_layer, width_cut, spacing_cut, enclosure_cut)
	Computes the maximal number of cuts to be placed on a layer of width width_layer considering specifications such as the spacing between the cuts, its width and its enclosure in the layer.
	cutLine (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutNumber, direction)
	Creates a horizontal or vertical line of contacts according to the specified direction.
	cutMatrix (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutColumnNumber, cutRowNumber)
	Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts.
	getBottomPlateYMax (self)
	getBottomPlateLeftCutXMin (self)
	getBottomPlateLeftCutYMin (self)
	getBottomPlateLeftCutYMax (self)
	getBottomPlateRightCutXMin (self)
	getBottomPlateRightCutYMin (self)
	getBottomPlateRightCutYMax (self)
	getBotPlateLeftRLayerXMax (self)
	getBottomPlateRightCutYCenter (self)
	getBotPlateLeftRLayerXMin (self)
	getBotPlateRLayerYMin (self)
	getBotPlateRLayerYMax (self)
	getBotPlateRLayerWidth (self)
	getBotPlateRightRLayerXCenter (self)
	getBotPlateLeftRLayerXCenter (self)
	getTopPlateRLayerYMin (self)
	getTopPlateRLayerYMax (self)
	getTopPlateRLayerWidth (self)
	getTopPlateRLayerXCenter (self)
	getTopPlateRLayerXMin (self)
	getTopPlateRLayerXMax (self)

Detailed Description

Route two matched capacitors, C1 and C2, drawn in a capacitor matrix.

Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2. Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions , the total number of vertical tracks is equivalent to couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.

Layout

An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.

Member Function Documentation

__setStretching__()

__setStretching__

(

self

)

Sets vertical stretching value considering spacing between elementary capacitors in the matrix.

Returns

stratching value.

References CapacitorStack.abutmentBox_spacing.

Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and drawVRoutingTracks().

setRules()

setRules

(

self

)

Defines technology rules used to draw the layout.

Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.

Remark:

All CapacitorStack class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported.

Returns

a dictionary with rules labels as keys and rules content as values.

Reimplemented from CapacitorStack.

Reimplemented in RoutMatchedCapacitor.

References minEnclosure_hRoutingLayer_vRoutingTrack_cut, minEnclosure_hRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingTrack, minSpacing_hRoutingTrack, minWidth_hRoutingLayer, RoutMatchedCapacitor.minWidth_hRoutingLayer_vRoutingTrack_cut, minWidth_hRoutingLayer_vRoutingTrack_cut, minWidth_hRoutingTrack, RoutMatchedCapacitor.minWidth_hRoutingTrackCut, and minWidth_hRoutingTrackCut.

create()

create

(

self

)

Draw the compact or matrix of capacitors.

First, . Second, . Finally, .

Reimplemented from CapacitorStack.

References capacitorInstance, CapacitorStack.capacitorsNumber, computeVRTDimensions(), drawVRoutingTracks(), minimizeVRTs(), and CapacitorUnit.setRules().

drawVRoutingTracks()

drawVRoutingTracks	(		self,
			vRoutingTracksLayer )

Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer.

Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]. As given in Figure 2, capacitor with an even j value situated in even columns have and inversely for odd columns numbers.

References __computeVRTsNumber__(), __findCapIdsToEliminate__(), __findCapIdsToEliminatePerColumn__(), __findUsedCapIdsPerColumn__(), __findVRTsToEliminate__(), __setNetsDistribution__(), __setPlatesDistribution__(), __setStretching__(), __setVRTsDistribution__(), CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.capacitorIds, capacitorIds, capacitorInstance, CapacitorStack.capacitorsNumber, computeXCenters(), CapacitorStack.dummyElement, CapacitorStack.dummyRing, getVTrackYMax(), getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingTrack_width, hRoutingTrack_width, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, RoutMatchedCapacitor.maximumPosition, maximumPosition, minEnclosure_hRoutingTrackCut, minimizeVRT, RoutMatchedCapacitor.minimumPosition, minimumPosition, minWidth_hRoutingTrack, RoutMatchedCapacitor.minWidth_hRoutingTrackCut, minWidth_hRoutingTrackCut, CapacitorStack.nets, platesDistribution, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackDict, vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackXCenter, vRoutingTrackXCenter, RoutMatchedCapacitor.vRTsDistribution, vRTsDistribution, and vRTsToEliminate.

Referenced by create().

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The documentation for this class was generated from the following file:

• capacitorvrtracks.py