| (Timing) Signal |
Point of the circuit where the timing propagation of the logical information is
measured. Whereas the logical signal is linked to a net, the timing signal is linked
to a node.
Indeed, as propagation delays in RC networks must be taken into account, it is necessary
to measure the
timing propagation of the logical information on several points of the net. The methodology
in HITAS is to associate
a timing signal with each terminal node of a net. As a result, several timing signals
may exist where only one
logical signal exist.
|
| Event |
Rising or falling logical transition on a timing signal |
| Reference point |
Timing signal where timing checks must be performed: input or output
connectors, latch, precharge, latch or precharge commands.
|
| Path |
List of timing signals, from reference point to reference point,
through which logical information is carried
|
| Break point |
User defined reference point |