# packages

pkgId: 9b7ec9dedc490a4c8a82b1718e4c30da35184d871eefe9855062aac8403fc982
name: coriolis-eda
arch: x86_64
version: 2.5.5
epoch: 0
release: 193.1.f4c1b74de
summary: Coriolis 2 EDA toolchain
url: https://coriolis.lip6.fr/
rpm_license: BSD-1-Clause AND LGPL-2.0-only AND GPL-2.0-only AND Apache-1.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: h02-ch1d
rpm_sourcerpm: coriolis-eda-2.5.5-193.1.f4c1b74de.src.rpm
rpm_packager: Mazher Iqbal <mazher@lip6.fr>
location_href: x86_64/coriolis-eda-2.5.5-193.1.f4c1b74de.x86_64.rpm
checksum_type: sha256
description:
  A FOSS EDA tool suite for physical design. Provides an integrated
  place & route for ASICs. Support symbolic layout (Alliance) and
  real layout (GDS). While mainly written in C++, it has an extensive
  Python interface.


pkgId: f07c093bbaff932e816d71c066c1e3b06df97dbc06d2c7760b242f730a67a8ca
name: coriolis-eda-doc
arch: noarch
version: 2.5.5
epoch: 0
release: 193.1.f4c1b74de
summary: Documentation of the Coriolis EDA toolchain
url: https://coriolis.lip6.fr/
rpm_license: BSD-1-Clause AND LGPL-2.0-only AND GPL-2.0-only AND Apache-1.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: h02-ch1d
rpm_sourcerpm: coriolis-eda-2.5.5-193.1.f4c1b74de.src.rpm
rpm_packager: Mazher Iqbal <mazher@lip6.fr>
location_href: noarch/coriolis-eda-doc-2.5.5-193.1.f4c1b74de.noarch.rpm
checksum_type: sha256
description:
  The documentation is a subset of the Coriolis website. It provides
  informations on:
  * The Hurricane database (C++).
  * The Coriolis Core (CRL) infrastructure (C++).
  * The dedicated C++/Python wrapper (Isobar,C/C++/Python). The Python
    interface has been made so that it mimics closely the C++ one, so
    the C++ doc can be used for both.
  * Some technical specifications.
  * A general introduction and user's manual.


pkgId: e2c981fe7b759fcdd23601172062f09774712be92d589a538a469789f837d8b2
name: libngspice
arch: x86_64
version: 44.2
epoch: 0
release: 1.1
summary: Shared libraries for ngspice
url: https://ngspice.sourceforge.io
rpm_license: BSD-2-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: System/Libraries
rpm_buildhost: i02-ch2c
rpm_sourcerpm: ngspice-44.2-1.1.src.rpm
location_href: x86_64/libngspice-44.2-1.1.x86_64.rpm
checksum_type: sha256
description:
  Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
  is based on three open source software packages: Spice3f5, Cider1b1
  and Xspice. This package contains the shared libraries.


pkgId: 23232d15bdbd90ce97b07e6372f65dd78b76cecca1e860f2eaf7ffecb4c556b8
name: libngspice-devel
arch: x86_64
version: 44.2
epoch: 0
release: 1.1
summary: Development files for ngspice
url: https://ngspice.sourceforge.io
rpm_license: BSD-2-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Development/Libraries/Other
rpm_buildhost: i02-ch2c
rpm_sourcerpm: ngspice-44.2-1.1.src.rpm
location_href: x86_64/libngspice-devel-44.2-1.1.x86_64.rpm
checksum_type: sha256
description:
  Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
  is based on three open source software packages: Spice3f5, Cider1b1
  and Xspice. This package contains the development files.


pkgId: b87ab680e3c05661f46cc03e5d78c9482fdc6e711b3b2ea4fb562588c7665ab4
name: ngspice
arch: x86_64
version: 44.2
epoch: 0
release: 1.1
summary: Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5
url: https://ngspice.sourceforge.io
rpm_license: BSD-2-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: i02-ch2c
rpm_sourcerpm: ngspice-44.2-1.1.src.rpm
location_href: x86_64/ngspice-44.2-1.1.x86_64.rpm
checksum_type: sha256
description:
  Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
  is based on three open source software packages: Spice3f5, Cider1b1
  and Xspice.


pkgId: e79e80c5ddd7fc39316b8178738e52f68764a5c8472c136c1f335e34b78040d6
name: openvaf
arch: x86_64
version: 23.5.0
epoch: 0
release: 5.1
summary: OpenVAF is a Next-Generation Verilog-A compiler
url: https://openvaf.semimod.de/
rpm_license: GPL-3.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i01-ch2c
rpm_sourcerpm: openvaf-23.5.0-5.1.src.rpm
location_href: x86_64/openvaf-23.5.0-5.1.x86_64.rpm
checksum_type: sha256
description:
  Circuit simulators play a critical role in the design of electrical circuits.
  Accurate simulations enable circuit designers to validate circuit behavior
  before actual fabrication happens, potentially saving significant re-design
  costs.  The simulation of a circuit critically depends on the so-called compact
  models and therefore:
  * The accuracy of the compact-model equations
  * The quality of the model parameters


pkgId: d8b8e3a68884305f16447510d93f053de3fe3dd946ef1d30646daae4992282d9
name: python3-coriolis-pdk-ihpsg13g2
arch: x86_64
version: 2024.10.15
epoch: 0
release: 27.1.bfa7190
summary: IHP Open PDK SG13G2
url: https://github.com/IHP-GmbH/IHP-Open-PDK
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Unspecified
rpm_buildhost: i04-ch4c
rpm_sourcerpm: coriolis-pdk-ihpsg13g2-2024.10.15-27.1.bfa7190.src.rpm
location_href: x86_64/python3-coriolis-pdk-ihpsg13g2-2024.10.15-27.1.bfa7190.x86_64.rpm
checksum_type: sha256
description:
  130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
  Signal and RF Design

  IHP Open  Source PDK project  goal is to  provide a fully  open source
  Process  Design Kit  and related  data, which  can be  used to  create
  manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
  repository is targeting the SG13G2 process node


pkgId: b3ef8eca963d91bd5e599bfbaa896d93736ac52bfe23ac91144e6e0c983b71e5
name: sv2v
arch: x86_64
version: 0.0.12
epoch: 0
release: 1.1
summary: sv2v - SystemVerilog to Verilog
url: https://github.com/zachjs/sv2v/
rpm_license: BSD-3-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i04-ch4c
rpm_sourcerpm: sv2v-0.0.12-1.1.src.rpm
location_href: x86_64/sv2v-0.0.12-1.1.x86_64.rpm
checksum_type: sha256
description:
  sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005),
  with an emphasis on supporting synthesizable language constructs.
    The primary goal of this project is to create a completely free and
  open-source tool for converting SystemVerilog to Verilog. While methods
  for performing this conversion already exist, they generally either rely
  on commercial tools, or are limited in scope.
    This project was originally developed to target Yosys, and so allows for
  disabling the conversion of (passing through) those SystemVerilog features
  that Yosys supports.


pkgId: 9847d831a094ead5c88a0ca92d845f27f2c69c221d98e24e17e5a6120cd89c0f
name: tas-yagle
arch: x86_64
version: 3.4.6
epoch: 0
release: 10.1.ea2ced1
summary: Tas/Yagle - Static Timing Analyser
url: https://coriolis.lip6.fr/
rpm_license: GPL-2.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i01-ch2a
rpm_sourcerpm: tas-yagle-3.4.6-10.1.ea2ced1.src.rpm
location_href: x86_64/tas-yagle-3.4.6-10.1.ea2ced1.x86_64.rpm
checksum_type: sha256
description:
  STATIC TIMING ANALYSIS
    The  advent   of  semiconductor  fabrication  technologies   now  allows  high
  performance in complex integrated circuits.
    With the increasing complexity of these circuits, static timing analysis (STA)
  has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
  performances are actually obtained.
    In addition, signal integrity (SI) issues due to crosstalk play a crucial role
  in performance and reliability of these  systems, and must be taken into account
  during the timing analysis.
    However, performance  achievement not  only lies in  fabrication technologies,
  but also  in the way circuits  are designed.  Very high  performance designs are
  obtained with semi or full-custom designs techniques.
    The HITAS platform provides advanced STA and SI solutions at transistor level.
  It has been  built-up in order to allow engineers to  ensure complete timing and
  SI coverage on their digital custom  designs, as well as IP-reuse through timing
  abstraction.
    Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
  full-chip verification, with virtually no limit of capacity in design size.


pkgId: 4d2df1e8fe31edb3b7dee87274fa68c476145a57b4b48c6f0c857f663f8bc913
name: yosys
arch: x86_64
version: 0.46
epoch: 0
release: 21.1.e97731b9d
summary: Yosys open synthesis suite
url: https://yosyshq.net/yosys/
rpm_license: ISC
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: h02-ch2b
rpm_sourcerpm: yosys-0.46-21.1.e97731b9d.src.rpm
location_href: x86_64/yosys-0.46-21.1.e97731b9d.x86_64.rpm
checksum_type: sha256
description:
  This is a framework for RTL synthesis tools. It currently has
  extensive Verilog-2005 support and provides a basic set of
  synthesis algorithms for various application domains.

  Yosys can be adapted to perform any synthesis job by combining
  the existing passes (algorithms) using synthesis scripts and
  adding additional passes as needed by extending the yosys C++
  code base.

  Yosys is free software licensed under the ISC license (a GPL
  compatible license that is similar in terms to the MIT license
  or the 2-clause BSD license).


