# packages

pkgId: b399a4b1d98d10c5487714c24acfc41a61c2f924b39bf718a5f246364d18eb71
name: coriolis-eda
arch: src
version: 2.5.5
epoch: 0
release: 193.2.f4c1b74de
summary: Coriolis 2 EDA toolchain
url: https://coriolis.lip6.fr/
rpm_license: BSD-1-Clause AND LGPL-2.0-only AND GPL-2.0-only AND Apache-1.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i02-ch2a
rpm_packager: Mazher Iqbal <mazher@lip6.fr>
location_href: src/coriolis-eda-2.5.5-193.2.f4c1b74de.src.rpm
checksum_type: sha256
description:
  A FOSS EDA tool suite for physical design. Provides an integrated
  place & route for ASICs. Support symbolic layout (Alliance) and
  real layout (GDS). While mainly written in C++, it has an extensive
  Python interface.


pkgId: 848c5dc0dccfadea9495624f250803276b9b33c24dc69f44b726bc5575772967
name: coriolis-pdk-ihpsg13g2
arch: src
version: 2024.10.15
epoch: 0
release: 27.10.bfa7190
summary: IHP Open PDK SG13G2
url: https://github.com/IHP-GmbH/IHP-Open-PDK
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Unspecified
rpm_buildhost: h02-ch1d
location_href: src/coriolis-pdk-ihpsg13g2-2024.10.15-27.10.bfa7190.src.rpm
checksum_type: sha256
description:
  130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
  Signal and RF Design

  IHP Open  Source PDK project  goal is to  provide a fully  open source
  Process  Design Kit  and related  data, which  can be  used to  create
  manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
  repository is targeting the SG13G2 process node


pkgId: 3612e124ef64d37a62495b5d917e76f4582011125848c341171b74e240af7a32
name: ngspice
arch: src
version: 44.2
epoch: 0
release: 1.4
summary: Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5
url: https://ngspice.sourceforge.io
rpm_license: BSD-2-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: i02-ch2b
location_href: src/ngspice-44.2-1.4.src.rpm
checksum_type: sha256
description:
  Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
  is based on three open source software packages: Spice3f5, Cider1b1
  and Xspice.


pkgId: 9e0300b9b7809f075bbfad3b3ac77ba9e003be3129aa8de3b3b065054cbe3886
name: openvaf
arch: src
version: 23.5.0
epoch: 0
release: 5.10
summary: OpenVAF is a Next-Generation Verilog-A compiler
url: https://openvaf.semimod.de/
rpm_license: GPL-3.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i03-ch2d
location_href: src/openvaf-23.5.0-5.10.src.rpm
checksum_type: sha256
description:
  Circuit simulators play a critical role in the design of electrical circuits.
  Accurate simulations enable circuit designers to validate circuit behavior
  before actual fabrication happens, potentially saving significant re-design
  costs.  The simulation of a circuit critically depends on the so-called compact
  models and therefore:
  * The accuracy of the compact-model equations
  * The quality of the model parameters


pkgId: f527d47d3e3c35eb8d0d040e33b28be80453b4b1cb1cbb7183bfd16d04f2dcc4
name: sv2v
arch: src
version: 0.0.12
epoch: 0
release: 1.4
summary: sv2v - SystemVerilog to Verilog
url: https://github.com/zachjs/sv2v/
rpm_license: BSD-3-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i02-ch1b
location_href: src/sv2v-0.0.12-1.4.src.rpm
checksum_type: sha256
description:
  sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005),
  with an emphasis on supporting synthesizable language constructs.
    The primary goal of this project is to create a completely free and
  open-source tool for converting SystemVerilog to Verilog. While methods
  for performing this conversion already exist, they generally either rely
  on commercial tools, or are limited in scope.
    This project was originally developed to target Yosys, and so allows for
  disabling the conversion of (passing through) those SystemVerilog features
  that Yosys supports.


pkgId: d4fca35d906d0889699505d396692ad2e0ac710cc410425e7f4b3fe250dfd509
name: yosys
arch: src
version: 0.46
epoch: 0
release: 21.10.e97731b9d
summary: Yosys open synthesis suite
url: https://yosyshq.net/yosys/
rpm_license: ISC
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i03-ch1c
location_href: src/yosys-0.46-21.10.e97731b9d.src.rpm
checksum_type: sha256
description:
  This is a framework for RTL synthesis tools. It currently has
  extensive Verilog-2005 support and provides a basic set of
  synthesis algorithms for various application domains.

  Yosys can be adapted to perform any synthesis job by combining
  the existing passes (algorithms) using synthesis scripts and
  adding additional passes as needed by extending the yosys C++
  code base.

  Yosys is free software licensed under the ISC license (a GPL
  compatible license that is similar in terms to the MIT license
  or the 2-clause BSD license).


